Stossbetrieb-SRAM zur Benutzung mit Hochgeschwindigkeitstakt

Burst SRAMs for use with a high speed clock

SRAM à accès à rafale pour utilisation avec horloge à haute vitesse

Abstract

Burst SRAMs designed for operation at a given data rate corresponding to the frequency of a first clock signal but capable of operation using a higher frequency clock signal. The burst SRAMs are preferably incorporated into the cache memory of a second level cache coupled to the processor bus in a computer system, where the computer system is preferably based on a 66-MHz P5 microprocessor. A cache controller, preferably incorporated within a memory controller, controls operation of the second level cache memory by providing the address load and address advance signals. The burst SRAMs are capable of recognizing the faster clock pulses, as well as the shorter pulses asserted on the address load and address advance signals. The address control signals are asserted and then negated during consecutive clock cycles of the faster clock signal, so that the burst SRAMs effectively operate at the same data rate corresponding to the lower frequency clock signal.

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Patent Citations (1)

    Publication numberPublication dateAssigneeTitle
    US-4631659-ADecember 23, 1986Texas Instruments IncorporatedMemory interface with automatic delay state

NO-Patent Citations (2)

    Title
    "improving the SRAM interface", ELECTRONIC ENGINEERING, vol. 63, no. 775, July 1991 (1991-07-01), LONDON GB, pages 51, XP000240133
    "optimum timing auto-configurable microcoded memory controller", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 33, no. 6A, November 1990 (1990-11-01), NEW YORK US, pages 269 - 272

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